The detailed operation of conventional Bandgap Reference (BGR) Core circuits, including the Current Mirror BGR (CM-BGR) and the Cascaded Current Mirror BGR (Cascaded CM-BGR), is discussed in this section. These architectures are analyzed in terms of their temperature compensation mechanisms, process variation tolerance.
Conventional BGR core
Integrated circuits (ICs) must operate reliably in harsh environmental conditions, ranging from hot desert temperatures to sub-zero polar temperatures. To operate stably under such conditions, a Bandgap Voltage Reference (BGR) Core has been designed to generate a temperature-independent reference voltage, as shown in Fig. 1. The BGR circuit is essential to maintain stable operation by demonstrating process independence, stable operation over different semiconductor fabrication processes, voltage independence, minimizing variations due to supply fluctuations, and temperature independence, to operate reliably over a broad temperature range, usually from − 40 to + 125 °C14. The basic principle behind a BGR circuit is the generation of two voltages with opposite temperature coefficients to attain thermal stability. One such voltage is the Complementary to Absolute Temperature (CTAT) voltage, derived from the base-emitter voltage (VBE) of a bipolar junction transistor (BJT). The VBE voltage is of negative temperature coefficient, reducing by about − 2 mV/°C with a rise in temperature15. This CTAT voltage, from a diode-connected BJT, forms the foundation for temperature compensation in BGR circuits to provide a stable reference voltage over changing environmental conditions16.
$$V_{BE1} = V_{T} {text{ ln}}left( {frac{{I_{C} }}{{I_{S} }}} right)$$
Band gap reference core circuit. A design using NPN transistor.
So, VBE is negative temperature co-efficient (− 2mv/°C).
The second one is PTAT Voltage (Proportional to Absolute Temperature). Derived from the thermal voltage (VT = kT/q), which increases linearly with temperature at a rate of approximately + 0.087 mV/°C. By scaling this voltage appropriately, its temperature coefficient can be matched to that of VBE. A PTAT voltage generator achieved by subtracting the VBE of two BJTs operating with a current density ratio N7.
$$V_{T} = frac{KT}{q} = frac{{1.32*10^{ – 23} *300left( {@room;temp} right)}}{{1.6*10^{ – 19} }},$$
So, VT is positive temperature co-efficient 0.087mv/°C)
$$begin{aligned} PTAT & = V_{BE1} – V_{BEn} \ & = V_{T} ;{text{ln}}left( {frac{{I_{C} }}{{I_{S} }}} right) – V_{T} ;{text{ln}}left( {frac{{{raise0.7exhbox{${I_{C} }$} !mathord{left/ {vphantom {{I_{C} } N}}right.kern-0pt} !lower0.7exhbox{$N$}}}}{{I_{S} }}} right) \ & = V_{T} ;{text{ln}}left( {{raise0.7exhbox{${left( {frac{{I_{C} }}{{I_{S} }}} right)}$} !mathord{left/ {vphantom {{left( {frac{{I_{C} }}{{I_{S} }}} right)} {left( {frac{{{raise0.7exhbox{${I_{C} }$} !mathord{left/ {vphantom {{I_{C} } N}}right.kern-0pt} !lower0.7exhbox{$N$}}}}{{I_{S} }}} right)}}}right.kern-0pt} !lower0.7exhbox{${left( {frac{{{raise0.7exhbox{${I_{C} }$} !mathord{left/ {vphantom {{I_{C} } N}}right.kern-0pt} !lower0.7exhbox{$N$}}}}{{I_{S} }}} right)}$}}} right) \ & = V_{T} ;{text{ln}}left( n right) \ end{aligned}$$
The sum of these voltages, appropriately weighted, yields a temperature-independent reference voltage.
The output reference voltage is given by.
VREF = VBE + VT⋅ln (N) = constant, which independent of PVT variations (when slope of CTAT = PTAT).
where ln (N) is a scaling factor determined by the ratio of slopes(m = 2/0.087 = 23). So, N should be very large in millions of transistors should be connected in the 2nd stage.
Robust cascaded current mirror-based Bandgap Reference (BGR) circuits
A conventional current mirror and a stable cascaded current mirror-based BGR circuit are analysed in this section for improving stability against variations of Process, Voltage, and Temperature (PVT)13,14,15. A single-stage BGR circuit based on current mirrors can be seen in Fig. 2a. The circuit consists of a PMOS current mirror (M1-M2) and a transistor-based BGR core (Q1-Q5). Temperature compensation is achieved by combining proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) voltages through the resistor RBGR.
Schematic and simulation results (a) CM-BGR (b) VBGR_OUT1 simulation for different RBGR values (c) cascaded CM-BGR (d) VBGR_OUT2 simulation for different RBGR values (e) The simulation results for the variation of BGR output against the variations of supply voltage.
The cascaded current mirror-based BGR17 with its robust structure shown in Fig. 2c is comprised of two additional current mirror stages (M11-M22 and M33-M44) to achieve better current replication. As a result, the output reference voltage (VBGROUT2) has enhanced immunity to supply variations.
Figure 2b, d illustrate the impact of RBGR variation on VBGROUT1 and VBGROUT2. Similarly, the Single-stage current mirror and the Cascaded current mirror have linear relationships between V_BGR and RBGR with varying sensitivity slopes, at 37.236 μV/Ω and 42.246 μV/Ω, respectively12. Due to the greater slope obtained in the cascaded current mirror structure, it may be possible to obtain proportional to absolute temperature compensation (PTAT) for smaller RBGR values.
The stability of BGR across an operating temperature range is shown through Fig. 2b, d. Figure 2e also shows how VBGR_OUT1 and VBGR_OUT2 with varying supplies (VDD) compared to each other. A stable bandgap reference (BGR) topology, by virtue of using cascaded current mirrors, has less sensitivity to the supply voltage noise. Supply voltage is changed from 0 to 4 V, simulations are carried at various process corners as well as over a − 40 °C and 125 °C temperature range making use of the 65 nm CMOS process.
Figure 3 shows the effect of startup resistance variations on the BGR circuit output and the startup transistor biasing characteristic13,16. In Fig. 3a, the BGR output voltage (VBGROUT1) is studied versus various startup resistance (Rs) values. For lower Rs values (regions S1 and S2), the output is shifted away from the expected value and remains at around 3.2 V, which shows proper startup functioning, due to improper biasing of NM4. Thus, it is operated in a linear region as given in Fig. 3c. Nevertheless, as Rs increases above a critical value (around 20kΩ), the BGR output begins producing a constant 1.3 V (from Fig. 3b) (regions S3 to S5), which indicates that the startup circuit successfully biases the BGR properly at high resistance values, when NM4 is biased to run in the saturation region. Figure 3c shows the biasing voltage (VGS) of the startup transistor NM4 versus different Rs values. At the beginning, NM4 is in the linear and saturation regions, allowing proper circuit startup. However, as Rs increases above a certain value, NM4 switches to the cutoff region, disabling the startup circuit and causing startup failure. This analysis verifies that choosing an optimum startup resistance is crucial in ensuring reliable BGR operation.
The BGR output (a) against the variations of startup resistance (b) with startup circuit (c) Biasing voltage of startup transistor (VNM4).
As shown in Fig. 4a, without the startup circuit, BGR fails to initialize correctly and stays in a metastable state, while with the startup circuit, it reaches the correct operating voltage of 1.3 V, as shown in Fig. 4b. A startup circuit is required to pull a small current at the beginning of operation in order to force the BGR into its correct operational state in Fig. 4c. Once the startup circuit is turned on, the startup transistor (NM4) pulls down on the VX4 node, which turns on the PMOS load transistors (M1, M4), taking the BGR from the zero-current state into the active operating region. During this stage, the biasing voltage VNM4 for the NM4 is very high which guarantees its conduction. The startup circuit must turn off once BGR settles so that unnecessary power dissipation does not take place when NM5 is turned on by a high potential at VX3, pulling down the N4 node, consequently turning NM4 off and ensuring that the startup circuit is disabled after initialization. After stabilization of the BGR core, the startup circuit acts as a normal turn-off circuit that prevents any unnecessary power from being consumed, as is seen from the startup transistor (INM4) reverting to zero at 120 µs.
The BGR output (a) without startup circuit (b) with startup (c) current through startup transistor (INM4).
Figure 5 presents the output occurrence graphs of CM-BGR and Cascaded CM-BGR under a supply sweep at 4 V. The results indicate that the Cascaded CM-BGR is able to maintain its target output voltage of 1.05 V, thus demonstrating its stability against supply changes. On the other hand, the CM-BGR demonstrates large deviations in its output voltage, tending towards higher supply levels in the samples. Such deviations indicate that the CM-BGR is more sensitive to supply changes, thus less stable.
Output occurrence plots of CM-BGR and cascaded CM-BGR.
BGR circuit design using operational amplifier
Operational amplifiers are used in applications where there is high gain and high speed. A differential input and differential output multi-stage configuration makes the circuit highly stable. With this configuration, differential signals are amplified and common-mode signals and noise are rejected simultaneously18. Differential inputs, V+ and V −, are connected to transistors M9 and M10 as shown in Fig. 6. A differential voltage can be translated into a differential current by these transistors, which form a differential pair. Transistors M1, M2, M3, and M4 also form the current mirror circuit, which provides the active load impedance of the differential pair.
Schematic of 2-stage operational amplifier.
The first stage consists of the differential pair (M5, M6) and the current mirror load (M1, M2). The gain of this stage is
$$begin{aligned} A1 & = gm5*R01 \ gm5 & = frac{{I_{D5} }}{{V_{OD5} }} \ R01 & = r05||r0p \ end{aligned}$$
A2 is the gain of the second stage (Common Source Amplifier)
$$begin{aligned} gm5 & = frac{{I_{D8} }}{{V_{OD8} }} \ R01 & = r08||r011 \ BW & = frac{{g_{M5} }}{2pi Cc} \ end{aligned}$$
(2)
Figure 7a, b illustrates how the phase response of the circuit changes when frequency is altered. Phase margin, or the phase shift from − 180°, is highly significant in establishing the stability of the amplifier.
$$PM = 180^{^circ } – tan^{ – 1} left( {frac{BW}{{f_{P2} }}} right)$$
(3)
Characteristics of operational amplifier (a). Phase response (b). Gain response between outputs to differential input nodes (c) gain response between cascading nodes (d) overall gain.
At differential gain, differential gain is the difference between the Vout gain and the gain of V+, V−, with intermediate nodes (Vy1, Vz1) considered. Ripples and peaks at high frequencies indicate parasitic effects or insufficient compensation. A sudden voltage gain vs. frequency spike in Fig. 7c might indicate resonances or noise coupling within the circuit. A plot of CMRR (Fig. 7d) illustrates the difference between the differential signal and the interference resulting from common-mode signals. The higher the CMRR, the higher the rejection by a differential amplifier of common-mode signals and noise.
A BGR circuit generates stable voltage that is independent of temperature, supply voltage, and process variations. Q1, Q2, Q3, Q4, Q5 and Q6 generates the CTAT voltages (VBE1, VBE2). R1 determines the current I1, which is proportional to the voltage difference VBE1–VBE2. R2 scales the PTAT current to generate the required voltage at the output. The operational amplifier enforces a virtual short condition, ensuring that the voltages at its inputs are equal19.
Operational Amplifier-based Bandgap Reference (BGR) circuit functions based on the production of a process-insensitive and temperature-stable reference voltage7,20,21. The operational principle of this circuit is the integration of two voltage terms with opposite temperature coefficients: the base-emitter voltage (VBE) of a bipolar junction transistor (BJT), with a negative temperature coefficient, and thermal voltage (Vt)7. The nomenclature is derived from the resistor network that exhibits a positive temperature coefficient. The operational amplifier provides for proper biasing by equating the voltages at its input terminals (VBE1, VX), thus ensuring the desired current flow through the BJT network as shown in the Fig. 8a. The current is copied across multiple transistors (M0, M1, M2) to provide a voltage proportional to absolute temperature (PTAT), which is then added to the complementary-to-absolute-temperature (CTAT) results, producing an effectively temperature-insensitive output voltage. The resistive ratio determines the PTAT voltage value, allowing precise reference voltage adjustment, typically to 1.2 V. MOSFET-based current sources offer a stable bias condition, with minimal supply voltage sensitivity. Figure 8b shows the relation between RBGR and slope of VBGROUT3 for the range of temperature − 40 °C to 125 °C. RBGR is adjusted to 139KΩ bring PTAT strength which equals to CTAT. The simulation results demonstrate the range of RBGR for which slope of VBGROUT3 is constant22.
$$begin{aligned} V_{BGROUT3} & = V_{BE3} + frac{{R_{BGR} }}{{R_{1} }}left( {V_{BE1} – V_{BE2} } right) \ V_{BGROUT3} & = V_{BE3} + frac{{R_{BGR} }}{{R_{1} }}left( {V_{T} *ln left( N right)} right) \ end{aligned}$$
(4)
(a) Band Gap reference circuit design1 using single operational amplifier (b) VBGR_OUT3 simulation for different RBGR values.
Sub-BGR circuit design using operational amplifier
The circuit shown in Fig. 9a is a sub-BGR, which produces constant reference voltage through current summing technique5,9. The sub-BGR is achieved using bipolar junction transistors (BJTs) (Q1–Q5) to produce base-emitter voltages (VBE) with negative temperature coefficient (CTAT). The R1 resistor is used to produce a current with positive temperature coefficient, since the differential CTAT voltage (VBE1–VBE2) produces a voltage drop across it, which essentially produces a proportional-to-absolute-temperature (PTAT) current. Since VX is a CTAT voltage, the voltage drops across R2 produces a CTAT current. The sum of PTAT and CTAT currents flow through M1 to make the resulting overall current constant23. M2 mirrors the constant current to resistor R0, where the combined CTAT and PTAT components produce a stable reference voltage at VBGROUTC1. A PMOS current mirror (M1) supplies stable bias currents to facilitate proper circuit operation. An operational amplifier keeps equal voltages (VBE1 and VX) at its inputs to facilitate proper generation of the PTAT current. The PTAT current, produced by the difference between the base-emitter voltages (VBE1 and VBE2) of the BJTs and scaled by resistor R1, is summed up with the CTAT current at the output node to facilitate temperature-compensated reference current24. This current, when passed through RBGR, produces a stable output voltage (VBGROUTC1).
(a) Sub-BGR circuit design1 using Operational Amplifier (b) VBGR_OUTc1 simulation for different RPTAT values.
Figure 9b plots the output voltage (VBGROUTC1) variation with temperature for different RPTAT values, which reflects the effect of RPTAT on temperature stability and the operation of the bandgap reference. The ideal bandgap reference should have a stable output voltage irrespective of the temperature change, with proper temperature compensation19. When RPTAT is scaled PTAT behavior is dominated and slope of output voltage (VBGROUTC1) is also changes, thus RPTAT is determined based on the VBGROUTC1 slope.