The semiconductor industry has relied on a simple equation for more than five decades — shrink the transistor, pack more onto every wafer, and watch performance soar as costs plummet. While each new node delivered predictable gains in speed, power efficiency, and density, that formula is rapidly running out of steam.
As transistors approach single-digit nanometer processes, manufacturing costs are spiking, not falling. Power delivery is turning into a bottleneck of speed versus thermal control, and the automatic performance boosts that defined Moore’s Law are diminishing.
To maintain progress, chipmakers have begun looking up — literally. Instead of building everything on a single plane, they are stacking logic, power, and memory vertically. While 2.5D packaging already has brought some of this into production, placing dies side-by-side on an interposer, imec’s CMOS 2.0 proposal goes further. It creates a wafer-scale layer cake of specialized tiers, each optimized for its function and connected through ultra-dense interconnects.
The appeal is obvious. A 3D system-on-chip could deliver more bandwidth, higher density, and lower energy consumption without relying solely on ever-smaller transistors. But the challenges are just as significant. Aligning wafer layers to sub-micron tolerances, managing thermal stress, and rethinking every stage of design and manufacturing will require a level of coordination the industry has never attempted before.
Meanwhile, the demand for compute power is accelerating. AI training workloads, advanced analytics, and pervasive connectivity are pushing data centers and device makers to search for new ways to sustain growth.
“The next era will not be defined by smaller transistors alone,” said Luc Van den hove, president and CEO of imec, during a presentation at ITF World. “It will be about integrating functions in three dimensions to overcome the bottlenecks of two-dimensional scaling.”
CMOS 2.0 is both straightforward and radical. The basic idea is to split the chip into layers, perfect each one independently, and bond them together as if they were a single monolithic device. In theory, it’s the next step beyond nanosheets. In practice, it will test whether the industry can scale complexity as effectively as it once scaled transistors.
What is CMOS 2.0?
At its core, CMOS 2.0 is an effort to move beyond the limitations of a single monolithic die. Rather than integrating logic, memory, and analog blocks on the same plane, each tier is fabricated independently and optimized for its role before being stacked into a unified assembly.
The approach combines four primary concepts:
- Backside power delivery, which relocates the power rails from the frontside metal stack to the rear of the wafer. This reduces IR-drop and frees routing resources for signals instead of power distribution.
- Fine-pitch hybrid bonding, which connects stacked tiers using copper-to-copper interconnects at scales far smaller than traditional microbumps.
- Complementary FETs (CFETs), which stack n- and p-type transistors vertically to shrink standard cell height and improve density.
- Bi-facial processing, which allows designers to build contacts, vias, and even transistors on both sides of a wafer. This creates new routing and integration options.
In principle, this layered architecture enables much shorter signal paths and higher bandwidth between logic and memory, while also improving energy efficiency by reducing parasitic losses. The vision is to create a system that functions more like a 3D network-on-chip than a flat assembly of blocks connected by long wires.
While some of these ideas may sound similar to 2.5D integration, such as chiplets mounted on interposers, there are important differences. In 2.5D packaging, known-good dies are placed side by side and connected through redistribution layers or silicon bridges. This approach improves I/O density and enables heterogeneous integration, but each die remains a discrete entity, often with its own package and separate power distribution. CMOS 2.0, by contrast, aims for true wafer-scale stacking, where tiers are bonded face-to-face (or face to back) in a monolithic structure and interconnected at a much finer pitch. The result is effectively one large die assembled vertically rather than horizontally.
“It is no longer enough to scale the transistor. We need to scale the system in all dimensions,” said Van den Hove. “By integrating different functions vertically, we can keep improving density and power without only relying on gate-length reductions.”
Fig. 1: imec CEO Luc Van den Hove shows 3D stack at ITF World. Source: Semiconductor Engineering/Gregory Haley
This distinction has significant implications for performance, cost, and manufacturability. While 2.5D systems can re-use existing process flows and test infrastructure, CMOS 2.0 requires rethinking everything from wafer thinning and bonding to thermal management and EDA tools. Each layer must be precisely aligned, bonded without voids, and verified in-line to avoid compounding yield losses.
“The idea is to treat the wafer as a platform that you can build in multiple layers, each with its own optimal technology,” said Julien Ryckaert, vice president of R&D at imec. “It means you can use different nodes, different design rules, and different materials in each tier to get the best performance and cost.”
Although hybrid bonding and backside power delivery have been demonstrated in test vehicles, combining them with vertical CFETs and bi-facial processing introduces substantial complexity. For most fabs, this represents not just a process change, but a fundamental shift in how chips are conceived, designed, and brought to volume production.
CMOS 2.0 advantages
While the idea of stacking wafers sounds simple, each of the four technology pillars behind CMOS 2.0 represents a major departure from conventional semiconductor manufacturing. Together, these pillars define the technical foundation of the approach and highlight why it is both promising and difficult to implement at scale.
Backside power delivery moves power rails to the backside of the wafer, enabling designers to clear valuable routing tracks on the frontside metal layers. This reduces IR-drop and improves timing closure, especially in dense standard cell arrays. Intel has already demonstrated a backside power architecture called PowerVia, and imec’s own backside contacts have shown significant reductions in voltage drop. However, integrating backside vias and metallization requires wafer thinning and specialized handling to prevent warpage and contamination.
Fine-pitch hybrid bonding is required to connect each stacked layer through copper-to-copper interconnects with far tighter spacing than traditional microbumps. While microbump pitches typically measure 40 to 50 microns, hybrid bonding targets less than 2 microns. This enables enormous bandwidth between tiers, but it demands near-perfect wafer alignment and surface preparation to avoid voids or open connections.
CFETs, meanwhile, build on the concept of gate-all-around transistors by stacking n- and p-type devices vertically. This configuration shortens the standard cell height by 30% to 40% and improves logic density without requiring smaller gate lengths. However, aligning the gates of both transistor types and integrating contacts through multiple layers adds complexity to lithography, deposition and etch steps.
The final development is bi-facial processing allows devices, contacts, and routing layers to be fabricated on both sides of the wafer. In a mature flow, this could enable additional power distribution, alternative interconnect schemes, or even functional devices on the backside. But bi-facial designs demand new process modules for wafer flipping, alignment, and metrology to maintain yield and performance.
Each of these pillars is technically feasible in isolation, but combining them in a single process flow is what makes CMOS 2.0 unique, and extremely difficult to implement. Yield management, process control, and design tool readiness will determine whether this vision can scale up to HVM.
Table 1: imec’s four pillars of CMOS 2.0. Source: imec
How CMOS 2.0 changes design rules
CMOS 2.0 does more than just reshape the process flow. It fundamentally alters how designers think about partitioning, routing, and verifying a system-on-chip. In conventional SoCs, floor-planning begins with a flat canvas of standard cells and a predictable stack of metal layers. Power distribution and signal routing are optimized together, with clear separation between front-end logic and back-end interconnect.
When multiple tiers are stacked in a monolithic assembly, many of these assumptions no longer apply. Designers have to decide early which blocks should live in which layers and how currents will flow vertically through backside vias. Instead of a single power grid, there are overlapping planes with different resistive paths and thermal constraints. Even something as basic as pin assignment becomes a three-dimensional problem, requiring tools that can model routing resources across multiple tiers.
“Partitioning across tiers is not just a floor-planning problem,” said Amlendu Shekhar Choubey, senior director at Synopsys. “It changes how you think about power delivery, signal integrity, and what needs to be tested at each phase. You have to consider these constraints from the very beginning or you will never close timing and yield.”
This shift also affects parasitic extraction. Shorter vertical interconnects can improve latency, but they introduce new capacitance-driven coupling effects that have to be modeled accurately. EDA workflows must account for thermal gradients across tiers, as hotspots in one layer can degrade performance or reliability in adjacent layers. Designers also need to understand how mechanical stress during bonding could impact device performance over time.
Place-and-route tools also need to evolve. Today’s engines are built on decades of assumptions about two-dimensional routing and standard cell rows. When tiers can be connected face-to-face at sub-micron pitch, routing becomes more like assembling a 3D mesh network. This demands new algorithms and design rules, as well as visualization tools that help engineers understand how their design performs in all three dimensions.
Beyond routing, sign-off and verification flows also must adapt. Multi-tier integration requires checking alignment tolerances, bond quality, and power integrity across multiple process steps. Thermal simulations must track how heat moves through different layers and whether localized hotspots can degrade performance. Without up-to-date modeling and analysis tools, the risk of compounding yield losses increases as more layers are added.
“EDA is no longer just chip design, said John Ferguson, senior director of product management at Siemens EDA. “It’s a holistic animal that spans concept to edge in-field data. That means modeling heat, stress, and electrical effects across tiers in a way that doesn’t kill turnaround time.”
Test and lifecycle telemetry are emerging as critical differentiators. In a multi-layer assembly, known-good-die economics become known-good-tiers, meaning each wafer-level layer must be tested and validated before bonding. The ability to monitor in-field reliability depends on embedding sensors deep inside the stack. Building an effective silicon lifecycle management strategy means incorporating test hooks and telemetry infrastructure at the earliest design stages.
“Test and silicon lifecycle management cannot be an afterthought,” said Synopsys’ Choubey. “In a vertical stack, you still need known-good dies and a path to field telemetry.”
This level of complexity also requires changes in how engineering teams collaborate. Traditional boundaries between chip design, packaging, and manufacturing are starting to blur as each discipline depends more heavily on the others. For many companies, this is not just a technical transition. It’s also a cultural one, requiring new workflows, skill sets, and partnerships.
“Splitting a system into different layers reduces the complexity of each subsystem, but it also adds complexity in how you connect them,” said WeiLii Tan, director of product management in Siemens EDA’s Custom IC Verification Division. “Now you have interrelated subsystems, and you have to figure out the best way to route between them.”
Manufacturing headwinds
While the vision for CMOS 2.0 is compelling, bringing it into high-volume production requires solving a long list of manufacturing challenges. Even individually, these obstacles are substantial.
Sub-micron hybrid bonding is perhaps the biggest technical challenge to overcome. Moving from microbumps with 40-micron pitches to copper-to-copper bonds under 2 microns requires wafer alignment accuracy below 100 nanometers. Any particles or surface roughness at the bonding interface can cause voids or electrical discontinuity. Even small process excursions can lead to yield losses that cascade across all tiers of the stack.
“Bond aligners currently provide sub-50 nanometer accuracy, which translates to less than 100 nanometers of wafer-to-wafer overlay accuracy,” said Bernd Dielacher, director of business development at EV Group. “That level of precision is vital to support imec’s interconnect scaling roadmap.”
Backside processing and wafer thinning add other challenges. To enable backside power delivery, wafers must be thinned to around 20 microns and processed with extreme care to avoid warpage and contamination. Handling ultra-thin substrates demands specialized carriers, temporary bonding adhesives, and cleaning steps that are not yet standardized.
“Handling ultra-thin wafers is a field of science on its own,” said Alice Guerrero, principal applications engineer at Brewer Science. “If you don’t control bow, warpage, and contamination perfectly, all the benefits of backside integration disappear.”
Process complexity and recipe management are also major challenges. Hybrid bonding and backside metallization require precise control over deposition, etch, and annealing steps. In many cases, the process window is so narrow that manual recipe tuning is no longer practical. This has driven an increasing reliance on machine learning to discover stable process conditions.
“When you look at a modern etch tool, you already have an astronomical number of recipes,” said Vahid Vahedi, chief technology and sustainability officer at Lam Research, during a presentation at ITF World. “The moment you add backside processing and hybrid bonding, the process space becomes so large that you need AI and advanced analytics to even find stable operating windows.”
Material integration and atomic-scale films present another layer of complexity. As devices stack vertically, any variation in film thickness or composition can impact alignment, yield, and long-term reliability. Selective deposition techniques, such as atomic layer deposition (ALD), are becoming critical to build uniform interfaces across the entire wafer surface.
“Every monolayer matters once devices go 3D,” said Hichem M’Saad, CEO of ASM, during a presentation at ITF World. “Selective ALD lets us self-align vias and maintain reliability for gate-all-around today and CFET tomorrow.”
Inspection and metrology
Finally, inspection and metrology must evolve. Traditional optical inspection struggles to see voids buried between bonded layers. While non-destructive methods — including infrared imaging and X-ray tomography — are being deployed to catch defects early, defect classification remains a bottleneck as process steps multiply and feature sizes shrink.
“Non-destructive inspection is essential for yield optimization,” said Dielacher. “If you can’t see the voids between layers early, this results in high scrap rates.”
Beyond final-stage metrology, manufacturers increasingly recognize the importance of catching potential wafer issues earlier in the process. Even modest warpage or bow can magnify during thinning and bonding, leading to alignment failures or partial voids that degrade yield.
The economic stakes are even higher when multiple good dies are stacked together. A single latent defect in one wafer can destroy the value of every other layer bonded on top of it. For this reason, some fabs are experimenting with more comprehensive macro inspection and excursion tracking much earlier to flag high-risk wafers before they enter the bonding flow.
“What they’re looking for is the greatest probability of chip integrity,” said Errol Akomer, director of applications at Microtronic. “If you see something early, you can guard-band it out before it ever becomes an expensive problem.”
In addition to improving yields, early inspection creates a detailed record of each wafer’s condition over time, enabling faster root-cause analysis when failures occur in the field.
“A lot of customers want an image of every wafer, multiple times throughout the line,” Akomer said. “If something goes wrong later, you can trace exactly where it started.”
These practices originated in high-reliability markets like automotive and aerospace, but they will become increasingly relevant for CMOS 2.0, where the cost and complexity of stacking multiple wafer tiers will make excursion control and traceability essential for economic viability.
Reliability economics
While CMOS 2.0 promises significant improvements in density and performance, it also creates new reliability and cost risks that are fundamentally different from planar scaling. One of the most important factors is yield stacking. In a monolithic wafer stack, every layer must meet specifications. If any tier fails, the entire assembly is lost. Even modest defect rates can compound across layers, driving effective yields to levels that challenge commercial viability.
Known-good-die strategies have been used for years in 2.5D and multi-chip modules, allowing manufacturers to screen individual dies before final assembly. With wafer-scale bonding, the focus shifts to known-good tiers. This requires rigorous in-line test and inspection at each build stage, as well as process monitoring to catch subtle variations before they propagate through the stack.
“With 50 tiles in an AI package, one bad GPU kills forty-nine good ones,” said Mark Gardener, fellow at Intel Foundry Services, during a presentation at ITF World. “Die-level sort and mid-flow test insertions become an extreme economic advantage.”
Beyond yield, field reliability becomes more complex. Thermal cycles, mechanical stress, and electromigration can impact different layers in different ways. Failure analysis is also more difficult because traditional probing and imaging techniques often cannot access buried tiers without destructive methods. As devices move into production, manufacturers will need new strategies to monitor in-field health and predict degradation over time.
Another economic consideration is whether the investment in 3D wafer stacking makes sense for all markets. While high-performance computing can absorb higher process costs to gain density and bandwidth, many other segments may find the economics prohibitive. Mature nodes will continue to play an important role, especially where cost, power, and reliability trump raw transistor density.
“Nodes like 130 nanometers and 22 nanometers aren’t legacy; they’re essential to electrification and RF,” said Gregg Bartlett, chief technology officer at GlobalFoundries, during a presentation at ITF World. “We’re probably not investing enough R&D below the glamour layer.”
For now, the economics of CMOS 2.0 likely will favor applications that can justify higher costs with premium performance and energy savings. But as process maturity improves, some of these benefits could migrate downstream, much as advanced packaging has begun to do over the past decade.
Competitive options
CMOS 2.0 is not the only strategy for extending scaling. Foundries and system companies are also investing heavily in alternative paths, each with its own set of benefits and trade-offs.
The most mature alternative is 2.5D integration using chiplets on interposers. This approach allows designers to disaggregate logic, memory, and analog functions into separate dies, then connect them side by side on a silicon or organic substrate. The benefit is flexibility. Each die can be fabricated on the most appropriate node, tested independently, and combined late in the flow. Known-good-die economics, established process tooling, and simpler yield management have made 2.5D attractive for applications ranging from high-end GPUs to networking ASICs.
However, 2.5D integration has its limits. Even with advanced redistribution layers and silicon bridges, the I/O density between chiplets is orders of magnitude lower than what hybrid bonding can achieve. Power delivery remains more complex, and signal latency increases as data traverses longer horizontal paths. For workloads that demand massive bandwidth and tight integration, 2.5D may not be sufficient.
The second alternative is monolithic scaling of CFET devices without wafer stacking. By combining n- and p-type gate-all-around transistors vertically, designers can reduce cell height and improve density without changing the integration model. This approach leverages existing process flows and avoids the alignment and bonding challenges of multi-tier assemblies. The tradeoff is that scaling eventually re-encounters the same interconnect and routing limits that CMOS 2.0 tries to solve by adding a third dimension.
Some companies are also exploring chiplet-based 3D integration that combines stacking with known-good-die methodologies, further blurring the line between packaging and monolithic design.
A final consideration is whether the infrastructure can keep pace with design and manufacturing complexity. As process nodes advance, the compute resources required for tape-out, OPC (optical proximity correction), and verification are growing exponentially. Even the most advanced EDA flows are under pressure as transistor counts surge.
“OPC compute is growing ten times every two years,” said Vivek Singh, vice president of advanced technology at NVIDIA, during a presentation at ITF World. “At that rate you’d need a hundred hyperscale data centers just for mask synthesis. Accelerated computing is how we tame that complexity beast.”
Table 2: Three paths to scaling beyond the nanosheet era. Source: Semiconductor Engineering/Gregory Haley
Choosing between these strategies will depend on product requirements, economic constraints, and ecosystem readiness. In many cases, the answer may not be either/or. Hybrid bonding, chiplets, and monolithic CFET scaling can coexist as complementary tools to extend Moore’s Law beyond the nanosheet era.
Outlook and milestones
Whether CMOS 2.0 becomes the next standard platform or remains an experimental niche will depend on how quickly its biggest hurdles can be resolved. In principle, the physics of wafer-scale stacking, backside power, and CFET integration are sound. In practice, the list of technical, economic, and logistical milestones is long.
First, sub-micron hybrid bonding must prove it can deliver reliable, void-free interconnects at scale. Yield management, in-line inspection, and process control will be critical to avoid compounding losses across tiers. Equipment makers and materials suppliers are already collaborating to refine surface preparation, bonding chemistries, and cleaning protocols.
“Hybrid bonding has moved from research to production, but reliable interconnect scaling below 1 micron depends on many factors such as perfect wafer preparation,” said Dielacher. “Too-high surface roughness, or any contamination, can ruin the interface, so the entire process flow has to be tightly controlled.”
Second, backside-aware EDA flows must mature. Place-and-route engines, timing sign-off tools, and power analysis frameworks will need to handle multi-tier connectivity without overwhelming designers. Simulation models must capture parasitic interactions, thermal gradients, and mechanical stress in ways that are credible and repeatable.
“EDA is not going to solve this in a vacuum,” said Joe Davis, senior director of product management at Siemens Digital Industries Software. “The ecosystem has to develop the methodologies and standards together, or the learning curve will be too steep.”
Third, materials and handling processes for ultra-thin wafers must become more robust. Warpage, bow, and contamination will have to be controlled to levels far beyond today’s standards.
“You can have the best design tools and process modules, but if the materials are not ready, none of it matters,” said Douglas Guerrero, senior technologist at Brewer Science. “Material readiness is the gatekeeper for everything else.”
Finally, the ecosystem must align. Equipment vendors, foundries, EDA providers, and IP suppliers will all have to agree on standards, workflows, and supply chains that can support CMOS 2.0 production. No single company can solve these challenges in isolation.
“CMOS 2.0 is not a transistor roadmap. It’s a system roadmap,” said imec’s Ryckaert. “The industry will have to decide if it wants to scale in two dimensions or three. If we can align, it opens a decade of innovation. If we can’t, we may be stuck.”
In the near term, CMOS 2.0 technology is most likely to appear in high-performance computing, AI accelerators, and premium mobile devices where density and bandwidth justify the investment. Over time, if yields improve and processes stabilize, it could migrate into broader markets.
For now, CMOS 2.0 offers a glimpse of what comes after the nanosheet era, and a reminder that scaling is no longer just about the transistor. It is about the entire system, stacked in layers, demanding new tools, new materials, and new thinking.
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